Quectel Commits RMB 430m to In-House Packaging Lines for SiP and FC-BGA, In Use From 2027

Quectel Wireless Solutions (SSE: 603236) said on 22 October that it has built up advanced packaging engineering capability around system-in-package (SiP) and flip-chip (FC) technologies, and is planning its own packaging lines with graded cleanrooms and mainstream packaging and test equipment, expected to be in use in 2027. Three days earlier, on 19 October, its board approved something more concrete: a reallocation of RMB 905 million of raised funds, of which RMB 430 million goes to an "advanced packaging manufacturing project". The press release describes a capability. The filing describes money, sites and a construction schedule. Together they show a module maker pulling the back-end process inside its own walls.

RMB 430 million buys capacity, not floor space

The filing published on 20 October puts the project at RMB 430.40 million in total investment, of which RMB 385.87 million comes from raised funds. The construction period is 24 months, the after-tax internal rate of return is 13.64% and the payback period 7.92 years. The investment breakdown is what reveals the nature of the spend:

• Equipment: RMB 310.05 million, 72.04% of the total. Site works: RMB 77.07 million, 17.91%. Contingency: RMB 19.36 million, 4.50%. Initial working capital: RMB 23.92 million, 5.56%.
• Sites: Shanghai, Changzhou in Jiangsu province and Ganzhou in Jiangxi province, executed by Quectel Wireless Solutions, Changzhou Quectel Communications Technology and Ganzhou Quectel Technology.
• Scope: purchase of production, inspection and test equipment to build advanced packaging lines covering RF front-end, Wi-Fi, GNSS and AI compute packaging.
• Status: approved by the board on 19 October, still subject to shareholder approval, after which filing and approval procedures follow.

Equipment at seven tenths of the budget and site works below one fifth means the money is buying process capability and line rhythm rather than square metres. The four packaging categories also map onto Quectel's product matrix: RF front-end, Wi-Fi, GNSS and AI compute are precisely the segments where cellular, short-range, positioning and compute modules are most constrained by packaging. The stated sequence is to serve existing cellular modules first, then high-value lines such as AI compute modules.

Why the money moved away from automotive

Where the funds came from matters as much as where they went. The original "automotive and 5G module capacity expansion project" was split. One part became a "5G module capacity expansion project" with RMB 539.02 million of total investment (RMB 518.91 million from raised funds), an 18-month build and a 12.96% after-tax IRR. The other part became the advanced packaging project. The reallocated amount totals RMB 904.79 million, or 40.58% of net raised funds.

The company's stated reason is a slowdown in global passenger-car demand and a wish to use the funds more efficiently, so it will no longer put raised money into automotive module lines. For the first half of 2026 Quectel reported revenue of RMB 15.259 billion and net profit attributable to shareholders of RMB 602 million. Read together, the three numbers describe two different bets: automotive module expansion bet on the slope of vehicle demand, packaging lines bet on a shift in product mix. Idle capacity from the first eats margin immediately; the second leaves design rules, process windows and yield know-how even if it ramps late. The reversibility of the two is not comparable, which is the most practical explanation for the redirection.

Why a module maker wants its own packaging

The press release frames the driver as convergence: 5G, satellite communications and on-device AI arriving at once force terminals to support multiple standards and bands in a fixed volume while integrating sensing, positioning, compute and radio, pushing modules toward smaller size, higher integration, lower power, better RF performance and higher reliability. Advanced packaging stops being a back-end step and becomes the path that decides system performance.

Inside the package, the approach is heterogeneous integration: an application processor, memory, RF transceiver and power management IC, together with filters, inductors and capacitors, co-integrated in a single package body. Against a discrete board-level design, micron-scale high-density interconnect shortens the distance between devices, a substrate cuts routing layers, and parasitic impedance, RF insertion loss and IR drop all fall while footprint and thickness shrink. In engineering terms this addresses three things at once: the RF front-end loss budget, power integrity and device thickness.

The filing lists the technical groundwork in more detail than the press release, and shows where the difficulty sits: multi-die heterogeneous integration, fine-pitch flip-chip bonding, warpage control on high-layer-count substrates, module EMI shielding and thermal management, and underfill reliability control for large FC-BGA packages. Process development covers shield-can attach, high-density placement of passives, heterogeneous die stacking, and for FC-BGA the flip-chip bond, copper pillar bumping, underfill, non-conductive film lamination, ball attach and substrate-level assembly. Quectel says it has brought in a team with experience at internationally recognised semiconductor companies, spanning R&D, process, equipment, process integration and product engineering. The barrier for a module maker is not any single step; it is the yield distribution once the steps are strung together.

Two different dates

The press release says the lines are expected to be in use in 2027. The filing says a 24-month construction period starting after shareholder approval. The two are not necessarily in conflict, but they describe different milestones: 2027 corresponds more closely to first equipment move-in and the start of process qualification, while the 24-month build describes the funded project as a whole. For customers planning by calendar year, that means samples and first small batches of in-house packaged modules in 2027, with volume supply more likely in 2028.

The filing also places uncertainty where it belongs. Key equipment and materials could face shortage, price increases, delivery delays or quality instability, affecting schedule, cost and delivery. And once built, a line still has to pass installation, process qualification, small-batch trial production and capacity ramp; if yield, reliability and efficiency improve more slowly than expected, capacity release and returns suffer. The stated mitigations are early supplier assessment and stocking aligned to equipment lead times, plus capacity release staged against process qualification, yield and order intake.

A secure die inside the package

One line in the press release is easy to skip: the lines will integrate secure dies inside the package, reducing exposed board-level contacts, strengthening resistance to physical teardown and lowering the risk of terminal opening and card-skimming fraud. That extends the value of advanced packaging from smaller and lower power to harder to open, and points directly at payment terminals — POS devices, scanners and self-checkout units that sit in public spaces for years. For those customers, once the traces between the secure element and the host move inside the package, the attack surface shifts from board level to package level, and certification attention moves from the bill of materials to package structure and teardown test reports.

Industry context: packaging moves to the centre

Quectel cites Yole's Status of the Advanced Packaging Industry 2026: the global advanced packaging market was worth about USD 55 billion in 2025, is expected to exceed USD 109 billion by 2031, a compound annual growth rate of roughly 12.08%. Yole's own release matches that framing — about USD 55 billion in 2025 to more than USD 109 billion in 2031 — and states that advanced packaging is overtaking traditional packaging to become the dominant segment of the semiconductor packaging industry.

Expansion at Chinese OSATs points the same way. Cailianshe reported on 21 August 2026 that JCET budgeted roughly RMB 10 billion of fixed asset investment for 2026, focused on advanced packaging lines, and plans RMB 7.8 billion for a high-end packaging plant in Lingang, Shanghai; Tongfu Microelectronics plans a private placement of up to RMB 4.22 billion, including RMB 620 million for high-performance computing and communications packaging capacity. A July tally by 21st Century Business Herald put packaging expansion announcements at close to RMB 40 billion for the year, concentrated in memory and advanced packaging. A module maker building its own line adds a captive back-end alongside the commercial OSATs; what it solves is not industry-wide capacity but its own place in the queue for high-value products.

HSY Perspective

What this line changes is not Quectel's capacity figure but the part-number structure of module distribution. The evidence sits in the investment breakdown: of RMB 430 million, RMB 310 million goes to equipment for RF front-end, Wi-Fi, GNSS and AI compute packaging, while the press release says the package body will co-integrate the application processor, memory, RF transceiver and power management together with filters, inductors and capacitors. Read together, a meaningful share of the board-level RF devices and passives once bought part by part moves inside the substrate and package. The buying entity shifts from the device maker and design house up to the module maker, and value migrates toward substrate and packaging capacity.

A timing mismatch follows. The funded project carries a 24-month construction period counted from shareholder approval, which is not the same milestone as "in use in 2027" in the press release, and the filing names equipment and material supply and yield ramp as its primary risks — the cost pressure of ramping arrives before any scale benefit. For customers already designed into Quectel modules, the observable change is in lead-time structure rather than price: supply rhythm moves from module-maker scheduling plus external OSAT queues to captive packaging capacity plus yield ramp, and allocation means something different.

The boundary of this judgment is clear. It holds if the lines serve captive cellular modules first and actually deliver yield on SiP and FC-BGA. If 2027 brings only equipment move-in with an unstable process window, depreciation and low yield raise module cost first, and vertical integration shows up as margin pressure before it shows up as advantage. If secure dies inside the package become standard for payment modules, standalone demand for board-level secure elements contracts in parallel — and that shift in enquiry structure will reach the channel earlier than any capacity number.

Sources: Quectel, "Quectel Continues to Advance Packaging Capability" (22 October 2026, quectel.com.cn); Quectel Wireless Solutions, announcement on changing part of the raised-fund investment projects (filed 20 October 2026); Yole Group, Status of the Advanced Packaging Industry 2026 and related release (about USD 55bn in 2025, more than USD 109bn by 2031); Cailianshe, 21 August 2026, on OSAT capacity expansion; 21st Century Business Herald, 15 July 2026, packaging expansion tally; Quectel Intelligent Manufacturing Center public materials (Changzhou, opened April 2023).