Pango Microsystems Shows Full-Stack AI Compute at WESEMiBAY 2026: Reconfigurable FPGA Matrix and PG3T1300 Accelerator Card
At WESEMiBAY 2026 in Shenzhen, Pango Microsystems showed its Titan, Kosmo, Logos and Compa FPGA families, a distributed reconfigurable AI inference matrix and the PG3T1300 accelerator card with PCIe 4.0 x8 and four 25G optical ports, winning the show's technical innovation award.
The 2026 Bay Area Semiconductor Ecosystem Expo (WESEMiBAY 2026) ran from 14 to 16 October at the Shenzhen Convention and Exhibition Centre. Pango Microsystems occupied the IC design and AI infrastructure zone with the full stack of its Titan, Kosmo, Logos and Compa FPGA families, alongside large-model inference solutions, domestically developed high-end accelerator cards and heterogeneous compute platforms. It also collected this year's WESEMiBAY Technical Innovation Award. What matters is not booth size: the company presented the entire chain from edge sensing through inference to core acceleration on one set of devices and one tool chain.
Four families, from board management to 1.3KK logic
The portfolio is layered by role. Titan targets high-performance FPGA: Titan-3 is built on FinFET, and the new PG3T1300 device reaches 1.3KK logic elements with high-speed DDR4/DDR5 memory interfaces, multi-rate EMAC hard cores, PCIe hard cores and high-speed SerDes, positioned publicly for communications, data centres, network security and image and video processing. Kosmo follows a CPU+FPGA+NPU heterogeneous architecture for highly integrated system-level designs. Logos covers cost-sensitive volume, and Compa supplies the CPLDs used for board management, control and IO expansion — a family the company says has already completed qualification and volume production with major data-centre server customers.
A fifth line, Visto-3, is still in development for very large designs, aimed at closing domestic gaps in next-generation communications, data centres, semiconductor equipment, SoC prototyping and EDA emulation acceleration. By the company's own count, five families span eight series and close to a hundred production part numbers.
A distributed reconfigurable FPGA matrix for large-model inference
The inference solution shown at the show is built around what Pango calls a distributed reconfigurable AI FPGA matrix. The stated value proposition is extreme TCO, hardware that can be reconfigured, hardware that tracks algorithm evolution, and support for million-token contexts and trillion-parameter models, aimed at enterprises and intelligent computing centres. The target problem is concrete: parameter counts have reached the trillions, deploying an unquantised model in an all-in-one appliance runs into memory bandwidth limits and an expensive supply chain, and inference workloads — unlike training — are judged on latency, energy efficiency and total cost of ownership rather than peak floating-point throughput.
Company engineers explained the approach at a concurrent forum: mixture-of-experts routing, memory bandwidth and load balancing are the hard parts, a distributed FPGA matrix can reshape data paths around expert routing, and FPGA clusters can exceed GPU energy efficiency by more than twofold on certain workloads while retaining ASIC-like efficiency and GPU-like flexibility. Those are vendor claims that need validation model by model and at real batch sizes, but the intent is clear: Pango no longer positions FPGA as prototype-validation silicon. It is bidding for inference compute budgets directly.
PG3T1300 accelerator card: interfaces built for movement
- Form factor: single-slot full-height half-length, with an integrated high-efficiency cooling structure
- Host interface: PCIe 4.0 ×8
- Network interfaces: four 25G optical ports, adaptable across 25G to 100G throughput tiers
- Silicon: Titan-3 PG3T1300 on FinFET, 1.3KK logic elements, DDR4/DDR5, multi-rate EMAC hard cores, PCIe hard cores, high-speed SerDes
- Stated applications: cloud virtualisation acceleration, image and video transcoding, high-frequency trading, storage acceleration, data acquisition and processing, large-model inference
The interface mix explains the design intent. PCIe 4.0 ×8 delivers roughly 15.75 GB/s in one direction, and four 25G ports total 100 Gbps, about 12.5 GB/s — the network side and host side sit in the same order of magnitude, so the card is built to let data pass through rather than accumulate. That ratio suits transcoding, capture and injection, storage acceleration and the middle tier of distributed inference; it does not suit training workloads that treat card memory as primary storage. For a data centre, a single-slot full-height half-length card with integrated cooling drops into an existing accelerator bay without reworking airflow.
Edge silicon: CPU, NPU and FPGA on one die
For edge inference Pango showed a high-performance, low-power multicore heterogeneous SoPC that integrates CPU, NPU and FPGA cores on a single die, paired with its own EDA tool chain. The pitch is low latency, data privacy, high bandwidth, low power and flexible interface types, supporting custom operators, multi-model deployment and continuous algorithm iteration across edge analytics, industrial vision, edge inference agents and edge compute cards. The architectural value is putting deterministic real-time control and neural inference on the same part, removing the round trip between host controller and accelerator.
Partner implementations are more concrete. Sipode's PG2K400-based heterogeneous card layers front-end FPGA parallel acceleration over back-end AI inference to reach millisecond-level real-time control for low-latency detection and tracking, panoramic vision for autonomous driving and industrial inspection. Xiaoyanjing Technology builds an 8–20 TOPS platform on PG2L200H for industrial inspection and intelligent transport. Alinx uses PG2K400 for in-vehicle video capture and injection, Hongcheng Optoelectronics demonstrates local dimming with colour enhancement, sharpening and histogram equalisation, and Shanghai Shenmuwei builds an industrial camera around PGL50H.
Market context: tight supply and inference-heavy workloads
The attention around domestic FPGA has clear external drivers. Securities Times reported that WESEMiBAY 2026 covered close to 80,000 square metres with more than 1,000 exhibitors, up 66% year on year, from 22 countries and regions; Science and Technology Daily's on-site report gives the same figures. On demand, MarketsandMarkets estimates the global FPGA market will grow from USD 11.73 billion in 2025 to USD 19.34 billion in 2030. Supply signals are blunter: from March 2026 AMD (Xilinx) and Lattice raised prices on mainstream products by 10–20%, lead times through the manufacturers have stretched to about 52 weeks, and spot prices in the channel have moved by multiples, according to TMTPost.
A structural shift is running alongside: inference now accounts for 70–80% of AI compute load, and the buying criteria have moved from peak throughput to latency, energy efficiency and total cost of ownership. That is FPGA territory, and it explains why Pango puts reconfigurability and TCO in the same sentence.
HSY Perspective
The real opening for domestic FPGA in this cycle is not replacing the highest-end part number but occupying the accelerator-card slot that server ecosystems have already standardised. A customer can wait for an equivalent device; if the slot does not fit, the architecture has to change. PCIe 4.0 ×8 in a single-slot full-height half-length card is a mainstream server specification, and four 25G ports match the data movement that distributed inference and video workloads demand. Parts that are interface-compliant first and compute-sufficient second meet far less resistance than a pin-compatible bid against a flagship FPGA.
The evidence is checkable on both sides. Overseas vendors raised mainstream prices by 10–20% from March 2026 with lead times around 52 weeks (TMTPost, 2026), pushing scheduling risk onto downstream buyers. Inference represents 70–80% of AI compute load, and procurement criteria have shifted to latency, efficiency and TCO. Pango itself lists six target applications for PG3T1300 — transcoding, capture, storage acceleration, high-frequency trading and inference among them — most of which are won on throughput and determinism rather than logic density. Together these point to orders landing first on cards that fit existing servers, not on flagship silicon.
The boundaries deserve stating. For training and very high-density inference, FPGA still loses to GPU and custom ASIC on cost per watt; the reconfiguration premium only holds where algorithms change quickly and volumes are modest. The claim of tracking algorithm evolution with day-zero adaptation is a vendor position, and whether customers can port operators onto Pango's own EDA chain depends on software maturity, not on device specifications. Titan-3 yield and delivery cadence are the variables that decide whether this route scales before 2027.